Verilog 转 Spice 网表

v2lvs 主要用于将 Verilog 网表转成 Spice 网表,一个典型的 v2lvs 例子如下所示。其中,第 2 ~ 3 行为 Verilog 代码输入,第 4 ~ 7 行为 Spice 网表输入,第 8 行为 Spice 网表输出。 v21vs -64 -sn \ -v ../../../../0UTPUT/TOP_TSCam.pg.v\ -v ./Pixel.pg.v \ -s /TOOLS/PDK/SMIC/SMIC55LL/SPDK55LL_ULP_09121825_OA_CDS_V1.16_2/smic5511_ulp_09121825_1P8M_6Ic_2TMc_ALPA1_oa_cds_v1.16_2/Calibre/LVS/empty_subckt.sp \ -s /TOOLS/STD_CELL/SMIC-55/SCC55NLL_HD_LVT_V2.0b/SCC55NLL_HD_LVT_V2p0b/cdl/SCC55NLL_HD_LVT_V2p0.cdl \ -s /TOOLS/STD CELL/SMIC-55/I0/SP55NLLD2RP OV3 VOp7/1vs/SP55NLLD2RP_OV3_VOp7.sp \ -s./SPAD.cdl \ -o TOP_TSCam.cdl 关于 v2lvs 更详细的指令介绍如下所示: -a <c1>[<c2>] : Change array delimiters from the default "[]". : c1 replaces left side '['. : c2 optionally replaces right side ']'. -addpin <pin> : Add <pin> to the signature of any Verilog module that does not have it. Connect <pin> to port <pin> in all instances that do not already have a connection specified. Spice libraries parsed with -lsr and -lsp will not have pins added -addpin is not compatitble with -i. -b : Preserve backslash character in escaped identifiers. -cb : Prefer CALDRCLVSEVE(Calibre CB) license during license search. -c <c1><c2> : Change illegal spice characters c1 to c2. -cfg <filename> : Config file for passing IP blocks related information. This will bring a custom spice file in to the Verilog and call a top level subckt from the Verilog. -e : Generate empty .SUBCKT statements (no instances are translated) -e is...

2022年6月27日 · 2 分钟 · 741 字 · Kai Wang